1. Technical Field
The present invention relates to a system and method for increasing error checking performance by calculating CRC values after multiple test patterns. More particularly, the present invention relates to a system and method to reduce verification time by sharing memory between multiple test patterns and performing memory error detection checks after each test pattern executes one time.
2. Description of the Related Art
A processor test team typically employs test patterns to verify and validate a system design. Processor testing tools exist whose goal is to generate the most stressful test pattern for a processor. In theory, the generated test pattern should provide maximum test coverage and should be interesting enough to stress various timing scenarios on the processor. The whole technology of these tools sits in the logic of building these test patterns.
Verifying and validating a processor using test patterns typically includes three stages, which are 1) test pattern build stage, 2) test pattern execution stage, and 3) validation and verification stage. Result comparison, such as CRC checks, plays a crucial role in the validation and verification stage. A challenge found, however, is that each result comparison requires a portion of the overall test cycle, which leaves less time for the test pattern execution stage.
What is needed, therefore, is a system and method that optimizes results checking in order to increase processor design verification and validation.